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CS51312 Synchronous CPU Buck Controller for 12 V Only Applications
The CS51312 is a synchronous dual NFET Buck Regulator Controller. It is designed to power the core logic of the latest high performance CPUs and ASICs from a single 12 V input. It uses the V2TM control method to achieve the fastest possible transient response and best overall regulation. It incorporates many additional features required to ensure the proper operation and protection of the CPU and Power system. The CS51312 provides the industry's most highly integrated solution, minimizing external component count, total solution size, and cost. The CS51312 is specifically designed to power Intel's Pentium(R) II processor and includes the following features: 5-bit DAC with 1.2% tolerance, Power-Good output, overcurrent hiccup mode protection, overvoltage protection, VCC monitor, Soft Start, adaptive voltage positioning, adaptive FET non-overlap time, and remote sense. The CS51312 will operate over a 9.0 V to 20 V (VCC2) range using either single or dual input voltage and is available in 16 lead narrow body surface mount package.
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16 1
SO-16 D SUFFIX CASE 751B
MARKING DIAGRAM
16 CS51312 AWLYWW 1 A WL, L YY, Y WW, W = Assembly Location = Wafer Lot = Year = Work Week
* * * * * * * * * * * * * *
Features Synchronous Switching Regulator Controller for CPU VCORE Dual N-Channel MOSFET Synchronous Buck Design V2 Control Topology 200 ns Transient Loop Response 5-Bit DAC with 1.2% Tolerance Hiccup Mode Overcurrent Protection 40 ns Gate Rise and Fall Times (3.3 nF Load) 65 ns Adaptive FET Non-Overlap Time Adaptive Voltage Positioning Power Good Output Monitors Regulator Output 5.0 V/12 V or 12 V-Only Operation VCC Monitor Provides Undervoltage Lockout OVP Output Monitors Regulator Output Multifunctional COMP Pin Provides ENABLE, Soft Start, and Hiccup Timing in Addition to Control Loop Compensation
PIN CONNECTIONS
1 VID0 VID1 VID2 VID3 VID4 VFB VOUT VCC1 16 COMP COFF PWRGD OVP GATE(L) GND GATE(H) VCC2
ORDERING INFORMATION
Device CS51312GD16 CS51312GDR16 Package SO-16 SO-16 Shipping 48 Units/Rail 2500 Tape & Reel
(c) Semiconductor Components Industries, LLC, 2001
1
January, 2001 - Rev. 2
Publication Order Number: CS51312/D
CS51312
12 V
D1 SS16GICT-ND
C1 1.0 F 12 V C2 C3 C4 R1 22 220 F
+ + +
16SV220 FY10AAJ-03A
C6 0.01 F
D2 ZM4746ACT-ND R2 200 C9 0.01 F R3 10 k
Q1
FY10AAJ-03A Q2 L1 1.2 H R4 0.004
C11 C12 C13 470 F 1.25 V to 3.5 V
+ + + + +
C10 1.0 F C19 1000 pF COFF
VCC2
VCC1 VFB GATE(H) GATE(L) FY10AAJ-03A Q3
COMP VID0 VID1 VID2 VID3 VID4 VOUT
C14
470 F T510X477K006AS4394 C15
CS51312 GND OVP PWRGD FY10AAJ-03A Q4
DAC ENABLE
D3 SS12GICT-ND
1 OVP 1 PWRGD
Figure 1. Application Diagram, 12 V to 16 A High Performance Converter
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CS51312
ABSOLUTE MAXIMUM RATINGS*
Rating Operating Junction Temperature, TJ Lead Temperature Soldering: Storage Temperature Range, TS ESD Susceptibility 1. 60 second maximum above 183C. *The maximum package power dissipation must be observed. Reflow: (SMD styles only) (Note 1.) Value 150 230 peak -65 to +150 2.0 Unit C C C kV
ABSOLUTE MAXIMUM RATINGS
Pin Name IC Bias and Low Side Driver Power Input IC High Side Driver Power Input Compensation Pin Voltage Feedback Input, Output Voltage Sense Pin, Voltage ID DAC Inputs Off-Time Pin High-Side FET Driver Low-Side FET Driver Power Good Output Overvoltage Protection Ground Pin Symbol VCC1 VCC2 COMP VFB, VOUT, VID0-4 VMAX 16 20 V 6.0 V 6.0 V VMIN -0.3 -0.3 V -0.3 V -0.3 V ISOURCE N/A N/A 1.0 mA 1.0 mA ISINK 1.5 A Peak, 200 mA DC 1.5 A Peak, 200 mA DC 5.0 mA 1.0 mA
COFF GATE(H) GATE(L) PWRGD OVP GND
6.0 V 20 V 16 V 6.0 V 15 V 0V
-0.3 V -0.3 V DC -0.3 V DC -0.3 V -0.3 V 0V
1.0 mA 1.5 A Peak, 200 mA DC 1.5 A Peak, 200 mA DC 1.0 mA 30 mA 1.5 A Peak, 200 mA DC
50 mA 1.5 A Peak, 200 mA DC 1.5 A Peak, 200 mA DC 30 mA 1.0 mA N/A
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ELECTRICAL CHARACTERISTICS (0C < TA < 70C; 0C < TJ < 125C; 9.0 V < VCC1 < 14 V; 9.0 V VCC2 20 V;
2.0 V DAC Code (VID4 = VID3 = VID2 = VID1 = 0, VID0 = 1.0) CGATE(H) = CGATE(L) = 3.3 nF, COFF = 390 pF; unless otherwise specified.) Characteristic Voltage Identification DAC Measure VFB = VCOMP, VCC = 12 V. Note 2. 755C 3 TJ 3 1255C VID4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 VID3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 VID2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 VID1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 VID0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 Min 3.483 3.384 3.285 3.186 3.087 2.989 2.890 2.791 2.692 2.594 2.495 2.396 2.297 2.198 2.099 2.050 2.001 1.953 1.904 1.854 1.805 1.755 1.706 1.656 1.607 1.558 1.508 1.459 1.409 1.360 1.310 1.225 Typ 3.525 3.425 3.325 3.225 3.125 3.025 2.925 2.825 2.725 2.625 2.525 2.425 2.325 2.225 2.125 2.075 2.025 1.975 1.925 1.875 1.825 1.775 1.725 1.675 1.625 1.575 1.525 1.475 1.425 1.375 1.325 1.250 Max 3.567 3.466 3.365 3.264 3.163 3.061 2.960 2.859 2.758 2.657 2.555 2.454 2.353 2.252 2.151 2.100 2.049 1.997 1.946 1.896 1.845 1.795 1.744 1.694 1.643 1.593 1.542 1.491 1.441 1.390 1.340 1.275 Tol 1.2% 1.2% 1.2% 1.2% 1.2% 1.2% 1.2% 1.2% 1.2% 1.2% 1.2% 1.2% 1.2% 1.2% 1.2% 1.2% 1.2% 1.1% 1.1% 1.1% 1.1% 1.1% 1.1% 1.1% 1.1% 1.1% 1.1% 1.1% 1.1% 1.1% 1.1% 2.0% Min 3.455 3.357 3.259 3.161 3.063 2.965 2.875 2.777 2.679 2.580 2.482 2.389 2.290 2.192 2.093 2.044 1.995 1.945 1.896 1.847 1.798 1.748 1.699 1.650 1.601 1.551 1.502 1.453 1.404 1.354 1.305 1.225 255C 3 TJ 3 755C Typ 3.525 3.425 3.325 3.225 3.125 3.025 2.925 2.825 2.725 2.625 2.525 2.425 2.325 2.225 2.125 2.075 2.025 1.975 1.925 1.875 1.825 1.775 1.725 1.675 1.625 1.575 1.525 1.475 1.425 1.375 1.325 1.250 Max 3.596 3.494 3.392 3.290 3.188 3.086 2.975 2.873 2.771 2.670 2.568 2.461 2.360 2.258 2.157 2.106 2.055 2.005 1.954 1.903 1.852 1.802 1.751 1.700 1.649 1.599 1.548 1.497 1.446 1.396 1.345 1.275 Tol 2.0% 2.0% 2.0% 2.0% 2.0% 2.0% 1.7% 1.7% 1.7% 1.7% 1.7% 1.5% 1.5% 1.5% 1.5% 1.5% 1.5% 1.5% 1.5% 1.5% 1.5% 1.5% 1.5% 1.5% 1.5% 1.5% 1.5% 1.5% 1.5% 1.5% 1.5% 2.0% Unit V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V Test Conditions
2. The IC power dissipation in a typical application with VCC = 12 V, switching frequency fSW = 250 kHz, 50 nc MOSFETs and RJA = 115C/W yields an operating junction temperature rise of approximately 52C, and a junction temperature of 77C with an ambient temperature of 25C.
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CS51312
ELECTRICAL CHARACTERISTICS (continued) (0C < TA < 70C; 0C < TJ < 125C; 9.0 V < VCC1 < 14 V; 9.0 V VCC2 20 V; 2.0 V DAC Code (VID4 = VID3 = VID2 = VID1 = 0, VID0 = 1.0) CGATE(H) = CGATE(L) = 3.3 nF, COFF = 390 pF; unless otherwise specified.)
Characteristic Voltage Identification DAC (continued) Line Regulation Input Threshold Input Pull-Up Resistance Pull-Up Voltage Error Amplifier VFB Bias Current COMP Source Current COMP Sink Current Open Loop Gain Unity Gain Bandwidth PSRR @ 1.0 kHz Transconductance Output Impedance GATE(H) and GATE(L) High Voltage at 100 mA Low Voltage at 100 mA Rise Time Fall Time GATE(H) to GATE(L) Delay GATE(L) to GATE(H) Delay GATE Pull-Down Overcurrent Protection OVC Comparator Offset Voltage Discharge Threshold Voltage VOUT Bias Current OVC Latch Discharge Current PWM Comparator PWM Comparator Offset Voltage Transient Response COFF Off-Time Charge Current Discharge Current VCOFF = 1.5 V VCOFF = 1.5 V - 1.0 - - 1.6 550 25 2.3 - - s A mA 0 V VFB 3.5 V VFB = 0 to 3.5 V 0.99 - 1.1 200 1.23 300 V ns 0.2 V VOUT 3.5 V VCOMP = 1.0 V 0 V VOUT 3.5 V - 77 0.2 -7.0 100 86 0.25 0.1 800 101 0.3 7.0 2500 mV V A A Measure VCC1/2 - GATE(L)/(H) Measure GATE(L)/(H) 1.6 V < GATE(H)/(L) < (VCC1/2 - 2.5 V) (VCC1/2 - 2.5 V) > GATE(L)/(H) > 1.6 V GATE(H) < 2.0 V, GATE(L) > 2.0 V, VCC1/2 = 12 V GATE(L) < 2.0 V, GATE(H) > 2.0 V, VCC1/2 = 12 V Resistance to GND. Note 3. - - - - 30 30 20 1.2 1.0 40 40 65 65 50 2.1 1.5 80 80 110 110 115 V V ns ns ns ns k 0.2 V VFB 3.5 V VCOMP = 1.2 V to 3.6 V, VFB = 1.9 V VCOMP = 1.2 V, VFB = 2.1 V CCOMP = 0.1 F CCOMP = 0.1 F CCOMP = 0.1 F - - -7.0 15 30 - - - - - 0.1 30 60 80 50 70 32 0.5 7.0 60 120 - - - - - A A A dB kHz dB mmho M 9.0 V VCC 14 V VID4, VID3, VID2, VID1, VID0 VID4, VID3, VID2, VID1, VID0 - - 1.0 25 5.48 0.01 1.25 50 5.65 - 2.4 100 5.82 %/V V k V Test Conditions Min Typ Max Unit
3. Guaranteed by design, not 100% tested in production.
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ELECTRICAL CHARACTERISTICS (continued) (0C < TA < 70C; 0C < TJ < 125C; 9.0 V < VCC1 < 14 V; 9.0 V VCC2 20 V; 2.0 V DAC Code (VID4 = VID3 = VID2 = VID1 = 0, VID0 = 1.0) CGATE(H) = CGATE(L) = 3.3 nF, COFF = 390 pF; unless otherwise specified.)
Characteristic Power Good Output PWRGD Sink Current PWRGD Upper Threshold PWRGD Lower Threshold PWRGD Output Low Voltage Overvoltage Protection (OVP) Output OVP Source Current OVP Threshold OVP Pull-Up Voltage General Electrical Specifications VCC1 Monitor Start Threshold VCC1 Monitor Stop Threshold Hysteresis VCC1 Supply Current VCC2 Supply Current Start-Stop No Load on GATE(H), GATE(L) No Load on GATE(H), GATE(L) - - 7.9 7.6 0.15 - - 8.4 8.1 0.3 9.5 2.5 8.9 8.6 0.6 16 4.5 V V V mA mA OVP = 1.0 V % of Nominal DAC Code IOVP = 1.0 mA, VCC1 - VOVP 1.0 5.0 - 10 8.5 1.1 25 12 1.5 mA % V VFB = 1.7 V, VPWRGD = 1.0 V % of Nominal DAC Code % of Nominal DAC Code VFB = 1.7 V, IPWRGD = 500 A 0.5 5.0 -12 - 4.0 8.5 -8.5 0.2 15 12 -5.0 0.3 mA % % V Test Conditions Min Typ Max Unit
PACKAGE PIN DESCRIPTION
PACKAGE PIN # SO-16 1, 2, 3, 4, 5 PIN SYMBOL VID0-VID4 FUNCTION Voltage ID DAC inputs. These pins are internally pulled up to 5.65 V if left open. VID4 selects the DAC range. When VID4 is high (logic one), the Error Amp reference range is 2.125 V to 3.525 V with 100 mV increments. When VID4 is low (logic zero), the Error Amp reference voltage is 1.325 V to 2.075 V with 50 mV increments. Error amp inverting input, PWM comparator non-inverting input, current limit comparator non-inverting input, PWRGD and OVP comparator input. Current limit comparator inverting input. Input power supply pin for the internal circuitry and low side gate driver. Decouple with filter capacitor to GND. Input power supply pin for the high side gate driver. Decouple with filter capacitor to GND. High side switch FET driver pin. Ground pin and IC substrate connection. Low side synchronous FET driver pin. Overvoltage protection pin. Drives high when overvoltage condition is detected on VFB. Power Good Output. Open collector output drives low when VFB is out of regulation. Off-Time Capacitor pin. A capacitor from this pin to GND sets the off time for the regulator. Error amp output. PWM comparator inverting input. A capacitor on this pin provides error amp compensation, and determines the Soft Start and hiccup timing. Pulling COMP below 1.1 V (typ) turns off both GATE drivers and shuts down the regulator.
6 7 8 9 10 11 12 13 14 15 16
VFB VOUT VCC1 VCC2 GATE(H) GND GATE(L) OVP PWRGD COFF COMP
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VFB 1.1 V + - EA - + Current Limit VOUT 86 mV + - + - - + + - 0.25 V COMP PWM COMP + - Off Time Discharge COMP R Q Fault Latch S COFF
VID0 VID1 VID2 VID3 VID4 DAC VCC2 GATE(H) UVLO VCC1
+ -
Nonoverlap Logic
+ - VCC
GATE(L)
OVP
PWRGD
GND
Figure 2. Block Diagram
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TYPICAL PERFORMANCE CHARACTERISTICS
150 125 100 75 50 25 0 VCC = 12 V TA = 25C Risetime (ns) 150 125 100 75 50 25 0 VCC = 12 V TA = 25C
Falltime (ns)
0
2000
4000
6000 8000 10000 12000 14000 16000 Load Capacitance (pF)
0
2000 4000
6000 8000 10000 12000 14000 16000 Load Capacitance (pF)
Figure 3. GATE(H) and GATE(L) Falltime vs. Load Capacitance
0.10 DAC Output Voltage Deviation (%) VCC = 12 V 0.05 Output Error (%)
Figure 4. GATE(H) and GATE(L) Risetime vs. Load Capacitance
0.10 0.05 0
0
-0.05 -0.10 VCC = 12 V TA = 25C VID4 = 0
-0.05
-0.10
-0.15 -0.20
1.325
1.425
1.475
1.525
1.575
1.625
1.775
1.875
2.025
1.375
1.675
1.725
1.825
1.925
0
20
40
60
80
100
120
Load Capacitance (pF)
DAC Output Voltage Setting (V)
Figure 5. DAC Output Voltage vs. Temperature, DAC Code = 00001
0.35 0.30 0.25 Output Error (%) 0.20 0.15 0.10 0.05
Figure 6. Percent Output Error vs. DAC Output Voltage Setting, VID4 = 0
0 -0.05 -0.10 -0.15 -0.20 2.125 2.325 2.425 2.525 2.625 2.725 2.225 2.825 2.925 3.025 -0.25 VCC = 12 V TA = 25C VID4 = 1 3.125 3.425 3.225 3.325 3.525
DAC Output Voltage Setting (V)
Figure 7. Percent Output Error vs. DAC Output Voltage Setting, VID4 = 1
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1.975
2.075
-0.15
CS51312
APPLICATIONS INFORMATION THEORY OF OPERATION
V2 Control Method
The V2 method of control uses a ramp signal that is generated by the ESR of the output capacitors. This ramp is proportional to the AC current through the main inductor and is offset by the value of the DC output voltage. This control scheme inherently compensates for variation in either line or load conditions, since the ramp signal is generated from the output voltage itself. This control scheme differs from traditional techniques such as voltage mode, which generates an artificial ramp, and current mode, which generates a ramp from inductor current. The V2 control method is illustrated in Figure 8. The output voltage is used to generate both the error signal and the ramp signal. Since the ramp signal is simply the output voltage, it is affected by any change in the output regardless of the origin of that change. The ramp signal also contains the DC portion of the output voltage, which allows the control circuit to drive the main switch to 0% or 100% duty cycle as required.
PWM Comparator GATE(H) - C + GATE(L) Output Voltage Feedback VFB
The main purpose of this `slow' feedback loop is to provide DC accuracy. Noise immunity is significantly improved, since the error amplifier bandwidth can be rolled off at a low frequency. Enhanced noise immunity improves remote sensing of the output voltage, since the noise associated with long feedback traces can be effectively filtered. Line and load regulation are drastically improved because there are two independent voltage loops. A voltage mode controller relies on a change in the error signal to compensate for a deviation in either line or load voltage. This change in the error signal causes the output voltage to change corresponding to the gain of the error amplifier, which is normally specified as line and load regulation. A current mode controller maintains fixed error signal under deviation in the line voltage, since the slope of the ramp signal changes, but still relies on a change in the error signal for a deviation in load. The V2 method of control maintains a fixed error signal for both line and load variation, since the ramp signal is affected by both line and load.
Constant Off-Time
Ramp Signal
Error Amplifier COMP Error Signal E
- +
Reference Voltage
To minimize transient response, the CS51312 uses a Constant Off-Time method to control the rate of output pulses. During normal operation, the Off-Time of the high side switch is terminated after a fixed period, set by the COFF capacitor. Every time the VFB pin exceeds the COMP pin voltage an Off-Time is initiated. To maintain regulation, the V2 Control Loop varies switch On-Time. The PWM comparator monitors the output voltage ramp, and terminates the switch On-Time. Constant Off-Time provides a number of advantages. Switch Duty Cycle can be adjusted from 0 to 100% on a pulse-by pulse basis when responding to transient conditions. Both 0% and 100% Duty Cycle operation can be maintained for extended periods of time in response to Load or Line transients.
Programmable Output
Figure 8. V2 Control Diagram
A change in line voltage changes the current ramp in the inductor, affecting the ramp signal, which causes the V2 control scheme to compensate the duty cycle. Since the change in inductor current modifies the ramp signal, as in current mode control, the V2 control scheme has the same advantages in line transient response. A change in load current will have an affect on the output voltage, altering the ramp signal. A load step immediately changes the state of the comparator output, which controls the main switch. Load transient response is determined only by the comparator response time and the transition speed of the main switch. The reaction time to an output load step has no relation to the crossover frequency of the error signal loop, as in traditional control methods. The error signal loop can have a low crossover frequency, since transient response is handled by the ramp signal loop.
The CS51312 is designed to provide two methods for programming the output voltage of the power supply. A five bit on board digital to analog converter (DAC) is used to program the output voltage within two different ranges. The first range is 2.125 V to 3.525 V in 100 mV steps, the second is 1.325 V to 2.075 V in 50 mV steps, depending on the digital input code. If all five bits are left open, the CS51312 enters adjust mode. In adjust mode, the designer can choose any output voltage by using resistor divider feedback to the VFB pin, as in traditional controllers. The CS51312 is specifically designed to meet or exceed Intel's Pentium II specifications.
Error Amplifier
The COMP pin is the output of the error amplifier. A capacitor to GND compensates the error amplifier loop. Additionally, the built in offset on the PWM Comparator
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non-inverting input provides the hiccup timing for the Overcurrent Protection, Soft Start function, and regulator output enable.
VCC2 Charge Pump
In order to fully turn on the high side NFET, a voltage greater than the input voltage must be applied to VCC2 to bias the GATE(H) driver. Referring to the application diagram on page 2; a simple charge pump circuit can be implemented for this purpose through capacitor C6, resistor R1, and diodes D1 and D2. The input voltage, less the drop in D1 is stored in C6 during the off-time period. When the high-side FET turns on, it drives the inductor switching node and C6 high causing Schottky diode D1 to reverse bias. The charge stored in C6 is transferred to VCC2 through R1. Zener diode D2 clamps the VCC2 voltage to 18 V to prevent the VCC2 from exceeding its 20 V Max rating (see Figure 9).
The Error Amp Capacitor connected to the COMP pin is charged by a 30 A current source. This capacitor must be charged to 1.1 V (typ) so that it exceeds the PWM comparator's offset before the V2 PWM control loop permits switching to occur. When VCC1 has exceeded 8.4 V and COMP has charged to 1.1 V, the upper Gate driver (GATE(H)) is activated, turning on the upper FET. This causes current to flow through the output inductor and into the output capacitors and load according to the following equation:
I + (VIN * VOUT) T L
Channel 1 - Charge Pump Switching Node (10 V/div) Channel 2 - VCC2 (10 V/div) Channel 3 - GATE(H) (10 V/div) Channel 4 - Inductor Switching Node (10 V/div)
GATE(H) and the upper NFET remain on and inductor current ramps up until the initial pulse is terminated by either the PWM control loop or the overcurrent protection. This initial surge of in-rush current minimizes startup time, but avoids overstressing of the regulator's power components. The PWM comparator will terminate the initial pulse if the regulator output exceeds the voltage on the COMP pin plus the 1.1 V PWM comparator offset prior to the drop across the current sense resistor exceeding the current limit threshold. In this case, the PWM control loop has achieved regulation and the initial pulse is then followed by a constant off time as programmed by the COFF capacitor. The COMP capacitor will continue to slowly charge and the regulator output voltage will follow it, less the 1.1 V PWM offset, until it achieves the voltage programmed by the DAC's VID input. The Error Amp will then source or sink current to the COMP cap as required to maintain the correct regulator DC output voltage. Since the rate of increase of the COMP pin voltage is typically set much slower than the regulator's slew capability, inrush current, output voltage, and duty cycle all gradually increase from zero. (See Figures 10 and 11).
Figure 9. VCC2 Charge Pump Operation (1.0 ms/div)
Startup
The CS51312 provides a controlled startup of regulator output voltage and features Programmable Soft Start implemented through the Error Amp and external Compensation Capacitor. This feature, combined with overcurrent protection, prevents stress to the regulator power components and overshoot of the output voltage during startup. As Power is applied to the regulator, the CS51312 Undervoltage Lockout circuit (UVL) monitors the ICs supply voltage (VCC1) which is typically connected to the +12 V input. The UVL circuit prevents the NFET gates from being activated until VCC1 exceeds the 8.4 V (typ) threshold. Hysteresis of 300 mV (typ) is provided for noise immunity.
Channel 1 - Regulator Input Voltage and VCC1 (10 V/div) Channel 2 - COMP (2.0 V/div) Channel 3 - Regulator Output Voltage (1.0 V/div)
Figure 10. Normal Startup (5.0 ms/div)
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CS51312
When driving large capacitive loads, the COMP must charge slowly enough to avoid tripping the CS51312 overcurrent protection. The following equation can be used to ensure unconditional startup:
ICHG I * ILOAD t LIM CCOMP COUT
where: ICHG = COMP Source Current (30 A typical); CCOMP = COMP Capacitor value (0.1 F typical); ILIM = Current Limit Threshold; ILOAD = Load Current during startup; COUT = Total Output Capacitance.
Channel 1 - VCC2 (10 V/div) Channel 2 - GATE(H) (10 V/div) Channel 3 - Inductor Switching Node (10 V/div) Channel 4 - Regulator Output Voltage (2.0 V/div)
Normal Operation
Figure 11. Normal Startup Showing Initial Pulse Followed by Soft Start (5.0 ms/div)
If the voltage across the Current Sense resistor generates a voltage difference between the VFB and VOUT pins that exceeds the OVC Comparator Offset Voltage (86 mV typical), the Fault latch is set. This causes the COMP pin to be quickly discharged, turning off GATE(H) and the upper NFET since the voltage on the COMP pin is now less than the 1.1 V PWM comparator offset. The Fault latch is reset when the voltage on the COMP decreases below the discharge threshold voltage (0.25 V typical). The COMP capacitor will again begin to charge, and when it exceeds the 1.1 V PWM comparator offset, the regulator output will Soft Start normally (see Figure 12).
During normal operation, Switch Off-Time is constant and set by the COFF capacitor. Switch On-Time is adjusted by the V2 Control loop to maintain regulation. This results in changes in regulator switching frequency, duty cycle, and output ripple in response to changes in load and line. Output voltage ripple will be determined by inductor ripple current and the ESR of the output capacitors
Transient Response
Channel 1 - Regulator Output Voltage (1.0 V/div) Channel 2 - COMP Pin (1.0 V/div) Channel 3 - VCC (10 V/div)
Figure 12. Startup with COMP Pre-Charged to 2.0 V (2.0 ms/div)
The CS51312 V2 Control Loop's 200 ns reaction time provides unprecedented transient response to changes in input voltage or output current. Pulse-by-pulse adjustment of duty cycle is provided to quickly ramp the inductor current to the required level. Since the inductor current cannot be changed instantaneously, regulation is maintained by the output capacitor(s) during the time required to slew the inductor current. Overall load transient response is further improved through a feature called "Adaptive Voltage Positioning". This technique pre-positions the output capacitors voltage to reduce total output voltage excursions during changes in load. Holding tolerance to 1.0% allows the error amplifiers reference voltage to be targeted +25 mV high without compromising DC accuracy. A "Droop Resistor" connects the Error Amps feedback pin (VFB) to the output capacitors and load and carries the output current. With no load, there is no DC drop across this resistor, producing an output voltage tracking the Error amps, including the +25 mV offset. When the full load current is delivered, a 50 mV drop is developed across this resistor. This results in output voltage being offset -25 mV low. The benefit of Adaptive Voltage Positioning is that additional margin is provided for a load transient before reaching the output voltage specification limits. When load current suddenly increases from its minimum level, the output capacitor is pre-positioned +25 mV. Conversely, when load current suddenly decreases from its maximum level, the output capacitor is pre-positioned -25 mV. For
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CS51312
best Transient Response, a combination of a number of high frequency and bulk output capacitors are usually used. PROTECTION AND MONITORING FEATURES
Overcurrent Protection Output Enable
On/off control of the regulator outputs can be implemented by pulling the COMP pins low. It is required to pull the COMP pins below the 1.1 V PWM comparator offset voltage in order to disable switching on the GATE drivers.
Adaptive FET Non-Overlap
A hiccup mode current limit protection feature is provided, requiring only the COMP capacitor to implement. The CS51312 provides overcurrent protection by sensing the current through a "Droop" resistor, using an internal current sense comparator. The comparator compares the voltage drop through the "Droop" resistor to an internal reference voltage of 86 mV (typical). If the voltage drop across the "Droop" resistor exceeds this threshold, the current sense comparator allows the fault latch to be set. This causes the regulator to stop switching. During this over current condition, the CS51312 stays off for the time it takes the COMP pin capacitor to discharge to its lower 0.25 V threshold. As soon as the COMP pin reaches 0.25 V, the Fault latch is reset (no overcurrent condition present) and the COMP pin is charged with a 30 A current source to a voltage 1.1 V greater than the VFB voltage. Only at this point the regulator attempts to restart normally by delivering short gate pulses to both FETs. This protection scheme minimizes thermal stress to the regulator components, input power supply, and PC board traces, as the over current condition persists. Upon removal of the overload, the fault latch is cleared, allowing normal operation to resume.
Overvoltage Protection
The CS51312 includes circuitry to prevent the simultaneous conduction of both the high and low side NFETs. This is necessary to prevent efficiency reducing "shoot-through" current from flowing from the input voltage to ground through the two NFETs. Prior to either GATE(H) or GATE(L) driving high, the other GATE must reach its low state. Since GATE rise and fall times vary with loading, this results in a variable delay from the start of turn-off until the start of turn-on (see Figure 13).
Overvoltage protection (OVP) is provided as result of the normal operation of the V2 control topology and requires no additional external components. The control loop responds to an overvoltage condition within 200 ns, causing the top MOSFET to shut off, disconnecting the regulator from its input voltage. This results in a "crowbar" action to clamp the output voltage and prevents damage to the load. The regulator will remain in this state until the overvoltage condition ceases or the input voltage is pulled low. Additionally, a dedicated Overvoltage protection (OVP) output pin (pin 13) is provided in the CS51312. The OVP signal will go high (overvoltage condition), if the output voltage (VCC(CORE)) exceeds the regulation voltage by 8.5% of the voltage set by the particular DAC code. The OVP pin can source up to 25 mA of current that can be used to drive an SCR to crowbar the power supply.
Power Good Circuit
Channel 1 - GATE(H) (5.0 V/div) Channel 2 - GATE(L) (5.0 V/div) Channel 3 - Inductor Switching Node (10 V/div)
Figure 13. Adaptive FET Non-Overlap (100 ns/div)
CS51312-BASED VCC(CORE) BUCK REGULATOR DESIGN EXAMPLE
Step 1: Definition of the Design Specifications
The Power Good pin (pin 14) is an open-collector signal consistent with TTL DC specifications. It is externally pulled up, and is pulled low (below 0.3 V) when the regulator output voltage typically exceeds 8.5% of the nominal output voltage. Maximum output voltage deviation before Power Good is pulled low is 12%.
The output voltage tolerance can be affected by any or all of the following reasons: 1. buck regulator output voltage setpoint accuracy; 2. output voltage change due to discharging or charging of the bulk decoupling capacitors during a load current transient; 3. output voltage change due to the ESR and ESL of the bulk and high frequency decoupling capacitors, circuit traces, and vias; 4. output voltage ripple and noise. Budgeting the tolerance is left up to the designer who must take into account all of the above effects and provide an
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output voltage that will meet the specified tolerance at the load. The designer must also ensure that the regulator component temperatures are kept within the manufacturer's specified ratings at full load and maximum ambient temperature..
Step 2: Selection of the Output Capacitors
ESRMAX = maximum allowable ESR. The actual output voltage deviation due to ESR can then be verified and compared to the value assigned by the designer:
DVESR + DIOUT ESRMAX
These components must be selected and placed carefully to yield optimal results. Capacitors should be chosen to provide acceptable ripple on the regulator output voltage. Key specifications for output capacitors are their ESR (Equivalent Series Resistance), and ESL (Equivalent Series Inductance). For best transient response, a combination of low value/high frequency and bulk capacitors placed close to the load will be required. In order to determine the number of output capacitors the maximum voltage transient allowed during load transitions has to be specified. The output capacitors must hold the output voltage within these limits since the inductor current can not change with the required slew rate. The output capacitors must therefore have a very low ESL and ESR. The voltage change during the load current transient is:
DVOUT + DIOUT ESL ) ESR ) tTR Dt COUT
Similarly, the maximum allowable ESL is calculated from the following formula:
ESLMAX + DVESL DI Dt
where: I/T = load current slew rate (as high as 20 A/s); VESL = change in output voltage due to ESL. The actual maximum allowable ESL can be determined by using the equation:
ESLCAP ESLMAX + Number of output capacitors
where ESLCAP = maximum ESL per capacitor (it is estimated that a 10 x 12 mm Aluminum Electrolytic capacitor has approximately 4.0 nH of package inductance). The actual output voltage deviation due to the actual maximum ESL can then be verified:
DVESL + ESLMAX Dt DI
where: IOUT / t = load current slew rate; IOUT = load transient; t = load transient duration time; ESL = Maximum allowable ESL including capacitors, circuit traces, and vias; ESR = Maximum allowable ESR including capacitors and circuit traces; tTR = output voltage transient response time. The designer has to independently assign values for the change in output voltage due to ESR, ESL, and output capacitor discharging or charging. Empirical data indicates that most of the output voltage change (droop or spike depending on the load current transition) results from the total output capacitor ESR. The maximum allowable ESR can then be determined according to the formula
ESRMAX + DVESR DIOUT
The designer now must determine the change in output voltage due to output capacitor discharge during the transient:
DVCAP + DI DtTR COUT
where: tTR = the output voltage transient response time (assigned by the designer); VCAP = output voltage deviation due to output capacitor discharge; I = Load step. The total change in output voltage as a result of a load current transient can be verified by the following formula:
DVOUT + DVESR ) DVESL ) DVCAP Step 3: Selection of the Duty Cycle, Switching Frequency, Switch On-Time (TON) and Switch Off-Time (TOFF)
where VESR = change in output voltage due to ESR (assigned by the designer). Once the maximum allowable ESR is determined, the number of output capacitors can be found by using the formula
Number of capacitors + ESRCAP ESRMAX
The duty cycle of a buck converter (including parasitic losses) is given by the formula:
V ) (VHFET ) VL ) VDROOP) Duty Cycle + D + OUT VIN ) VLFET * VHFET * VL
where: ESRCAP = maximum ESR per capacitor (specified in manufacturer's data sheet);
where: VOUT = buck regulator output voltage; VHFET = high side FET voltage drop due to RDS(ON); VL = output inductor voltage drop due to inductor wire DC resistance;
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VDROOP = droop (current sense) resistor voltage drop; VIN = buck regulator input voltage; VLFET = low side FET voltage drop due to RDS(ON).
Step3a: Calculation of Switch On-Time
The Switch On-Time (time during which the switching MOSFET in a synchronous buck topology is conducting) is determined by:
Duty Cycle TON + FSW
where: VIN = input voltage; VOUT = output voltage; tTR = output voltage transient response time (assigned by the designer); I = load transient. The inductor ripple current can then be determined:
V TOFF DIL + OUT L
where FSW = regulator switching frequency selected by the designer. Higher operating frequencies allow the use of smaller inductor and capacitor values. Nevertheless, it is common to select lower frequency operation because a higher frequency results in lower efficiency due to MOSFET gate charge losses. Additionally, the use of smaller inductors at higher frequencies results in higher ripple current, higher output voltage ripple, and lower efficiency at light load currents.
Step 3b: Calculation of Switch Off-Time
where: IL = inductor ripple current; VOUT = output voltage; TOFF = switch Off-Time; L = inductor value. The designer can now verify if the number of output capacitors from Step 2 will provide an acceptable output voltage ripple (1.0% of output voltage is common). The formula below is used:
DVOUT DIL + ESRMAX
The Switch Off-Time (time during which the switching MOSFET is not conducting) can be determined by:
TOFF + 1.0 * TON FSW
Rearranging we have:
ESRMAX + DVOUT DIL
The COFF capacitor value has to be selected in order to set the Off-Time, TOFF, above:
COFF + Period (1.0 * D) 3980
where: 3980 is a characteristic factor of the CS51312; D = Duty Cycle.
Step 4: Selection of the Output Inductor
where ESRMAX = maximum allowable ESR; VOUT = 1.0% x VOUT = maximum allowable output voltage ripple ( budgeted by the designer ); IL = inductor ripple current; VOUT = output voltage. The number of output capacitors is determined by:
Number of capacitors + ESRCAP ESRMAX
The inductor should be selected based on its inductance, current capability, and DC resistance. Increasing the inductor value will decrease output voltage ripple, but degrade transient response. There are many factors to consider in selecting the inductor including cost, efficiency, EMI and ease of manufacture. The inductor must be able to handle the peak current at the switching frequency without saturating, and the copper resistance in the winding should be kept as low as possible to minimize resistive power loss. There are a variety of materials and types of magnetic cores that could be used for this application. Among them are ferrites, molypermalloy cores (MPP), amorphous and powdered iron cores. Powdered iron cores are very commonly used. Powdered iron cores are very suitable due to their high saturation flux density and have low loss at high frequencies, a distributed gap and exhibit very low EMI. The inductor value can be determined by:
L+ (VIN * VOUT) DI tTR
where ESRCAP = maximum ESR per capacitor (specified in manufacturer's data sheet). The designer must also verify that the inductor value yields reasonable inductor peak and valley currents (the inductor current is a triangular waveform):
DI IL(PEAK) + IOUT ) L 2.0
where: IL(PEAK) = inductor peak current; IOUT = load current; IL = inductor ripple current.
DI IL(VALLEY) + IOUT * L 2.0
where IL(VALLEY) = inductor valley current.
Step 5: Selection of the Input Capacitors
These components must be selected and placed carefully to yield optimal results. Capacitors should be chosen to
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provide acceptable ripple on the input supply lines. A key specification for input capacitors is their ripple current rating. The input capacitor should also be able to handle the input RMS current IIN(RMS). The combination of the input capacitors CIN discharges during the on-time. The input capacitor discharge current is given by:
ICINDIS(RMS) + IL(PEAK)2 ) (IL(PEAK) IL(VALLEY)) ) IL(VALLEY)2 3.0
Once the total ESR of the input capacitors is known, the input capacitor ripple voltage can be determined using the formula:
VCIN(RMS) + ICIN(RMS) ESRCIN
D
where: VCIN(RMS) = input capacitor RMS voltage; ICIN(RMS) = total input RMS current; ESRCIN = total input capacitor ESR. The designer must determine the input capacitor power loss in order to ensure there isn't excessive power dissipation through these components. The following formula is used:
PCIN(RMS) + ICIN(RMS)2 ESRCIN
where: ICINDIS(RMS) = input capacitor discharge current; IL(PEAK) = inductor peak current; IL(VALLEY) = inductor valley current. CIN charges during the off-time, the average current through the capacitor over one switching cycle is zero:
ICIN(CH) + ICIN(DIS) D 1.0 * D
where: PCIN(RMS) = input capacitor RMS power dissipation; ICIN(RMS) = total input RMS current; ESRCIN = total input capacitor ESR.
Step 6: Selection of the Input Inductor
where: ICIN(CH) = input capacitor charge current; ICIN(DIS) = input capacitor discharge current; D = Duty Cycle. The total Input RMS current is:
ICIN(RMS) + (ICIN(DIS)2 D) ) (ICIN(CH)2 (1.0 * D))
The number of input capacitors required is then determined by:
I NCIN + CIN(RMS) IRIPPLE
where: NCIN = number of input capacitors; ICIN(RMS) = total input RMS current; IRIPPLE = input capacitor ripple current rating (specified in manufacturer's data sheets). The total input capacitor ESR needs to be determined in order to calculate the power dissipation of the input capacitors:
ESRCIN + ESRCAP NCIN
A common requirement is that the buck controller must not disturb the input voltage. One method of achieving this is by using an input inductor and a bypass capacitor. The input inductor isolates the supply from the noise generated in the switching portion of the buck regulator and also limits the inrush current into the input capacitors upon power up. The inductor's limiting effect on the input current slew rate becomes increasingly beneficial during load transients. The worst case is when the load changes from no load to full load (load step), a condition under which the highest voltage change across the input capacitors is also seen by the input inductor. The inductor successfully blocks the ripple current while placing the transient current requirements on the input bypass capacitor bank, which has to initially support the sudden load change. The minimum inductance value for the input inductor is therefore:
DV LIN + (dI dt)MAX
where: ESRCIN = total input capacitor ESR; ESRCAP = maximum ESR per capacitor (specified in manufacturer's data sheets); NCIN = number of input capacitors.
where: LIN = input inductor value; V = voltage seen by the input inductor during a full load swing; (dI/dt)MAX = maximum allowable input current slew rate. The designer must select the LC filter pole frequency so that at least 40 dB attenuation is obtained at the regulator switching frequency. The LC filter is a double-pole network with a slope of -2.0, a roll-off rate of --40 dB/dec, and a corner frequency:
fC + 1.0 2.0p LC
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where: L = input inductor; C = input capacitor(s).
Step 7: Selection of the Switching FET FET Basics
The use of the MOSFET as a power switch is propelled by two reasons: 1) Its very high input impedance; and 2) Its very fast switching times. The electrical characteristics of a MOSFET are considered to be those of a perfect switch. Control and drive circuitry power is therefore reduced. Because the input impedance is so high, it is voltage driven. The input of the MOSFET acts as if it were a small capacitor, which the driving circuit must charge at turn on. The lower the drive impedance, the higher the rate of rise of VGS, and the faster the turn-on time. Power dissipation in the switching MOSFET consists of 1) conduction losses, 2) leakage losses, 3) turn-on switching losses, 4) turn-off switching losses, and 5) gate-transitions losses. The latter three losses are proportional to frequency. For the conducting power dissipation rms values of current and resistance are used for true power calculations. The fast switching speed of the MOSFET makes it indispensable for high-frequency power supply applications. Not only are switching power losses minimized, but also the maximum usable switching frequency is considerably higher. Switching time is independent of temperature. Also, at higher frequencies, the use of smaller and lighter components (transformer, filter choke, filter capacitor) reduces overall component cost while using less space for more efficient packaging at lower weight. The MOSFET has purely capacitive input impedance. No DC current is required. It is important to keep in mind the drain current of the FET has a negative temperature coefficient. Increase in temperature causes higher on-resistance and greater leakage current. VDS(ON) should be low to minimize power dissipation at a given ID, and VGS should be high to accomplish this. MOSFET switching times are determined by device capacitance, stray capacitance, and the impedance of the gate drive circuit. Thus the gate driving circuit must have high momentary peak current sourcing and sinking capability for switching the MOSFET. The input capacitance, output capacitance and reverse-transfer capacitance also increase with increased device current rating. Two considerations complicate the task of estimating switching times. First, since the magnitude of the input capacitance, CISS, varies with VDS, the RC time constant determined by the gate-drive impedance and CISS changes during the switching cycle. Consequently, computation of the rise time of the gate voltage by using a specific gate-drive impedance and input capacitance yields only a rough estimate. The second consideration is the effect of the "Miller" capacitance, CRSS, which is referred to as CDG in the following discussion. For example, when a device is on, VDS(ON) is fairly small and VGS is about 12 V. CDG is
charged to VDS(ON) - VGS, which is a negative potential if the drain is considered the positive electrode. When the drain is "off", CDG is charged to quite a different potential. In this case the voltage across CDG is a positive value since the potential from gate-to-source is near zero volts and VDS is essentially the drain supply voltage. During turn-on and turn-off, these large swings in gate-to-drain voltage tax the current sourcing and sinking capabilities of the gate drive. In addition to charging and discharging CGS, the gate drive must also supply the displacement current required by CDG(IGATE = CDG dVDG/dt). Unless the gate-drive impedance is very low, the VGS waveform commonly plateaus during rapid changes in the drain-to-source voltage. The most important aspect of FET performance is the Static Drain-To-Source On-Resistance (RDS(ON)), which effects regulator efficiency and FET thermal management requirements. The On-Resistance determines the amount of current a FET can handle without excessive power dissipation that may cause overheating and potentially catastrophic failure. As the drain current rises, especially above the continuous rating, the On-Resistance also increases. Its positive temperature coefficient is between +0.6%/C and +0.85%/C. The higher the On-Resistance the larger the conduction loss is. Additionally, the FET gate charge should be low in order to minimize switching losses and reduce power dissipation. Both logic level and standard FETs can be used. Voltage applied to the FET gates depends on the application circuit used. Both upper and lower gate driver outputs are specified to drive to within 1.5 V of ground when in the low state and to within 2.0 V of their respective bias supplies when in the high state. In practice, the FET gates will be driven rail-to-rail due to overshoot caused by the capacitive load they present to the controller IC.
Step 7a: Selection of the Switching (Upper) FET
The designer must ensure that the total power dissipation in the FET switch does not cause the power component's junction temperature to exceed 150C. The maximum RMS current through the switch can be determined by the following formula:
IRMS(H) + IL(PEAK)2 ) (IL(PEAK) IL(VALLEY)) ) IL(VALLEY)2 3.0
D
where: IRMS(H) = maximum switching MOSFET RMS current; IL(PEAK) = inductor peak current; IL(VALLEY) = inductor valley current; D = Duty Cycle.
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Once the RMS current through the switch is known, the switching MOSFET conduction losses can be calculated:
PRMS(H) + IRMS(H)2 RDS(ON)
where: PRMS(H) = switching MOSFET conduction losses; IRMS(H) = maximum switching MOSFET RMS current; RDS(ON) = FET drain-to-source on-resistance The upper MOSFET switching losses are caused during MOSFET switch-on and switch-off and can be determined by using the following formula:
PSWH + PSWH(ON) ) PSWH(OFF) V + IN IOUT (tRISE ) tFALL) 6.0T
D = Duty Cycle; RDS(ON) = lower FET drain-to-source on-resistance. The synchronous MOSFET has no switching losses, except for losses in the internal body diode, because it turns on into near zero voltage conditions. The MOSFET body diode will conduct during the non-overlap time and the resulting power dissipation (neglecting reverse recovery losses) can be calculated as follows:
PSWL + VSD ILOAD non-overlap time FSW
where: PSWH(ON) = upper MOSFET switch-on losses; PSWH(OFF) = upper MOSFET switch-off losses; VIN = input voltage; IOUT = load current; tRISE = MOSFET rise time (from FET manufacturer's switching characteristics performance curve); tFALL = MOSFET fall time (from FET manufacturer's switching characteristics performance curve); T = 1/FSW = period. The total power dissipation in the switching MOSFET can then be calculated as:
PHFET(TOTAL) + PRMSH ) PSWH(ON) ) PSWH(OFF)
where: PSWL = lower FET switching losses; VSD = lower FET source-to-drain voltage; ILOAD = load current Non-overlap time = GATE(L)-to-GATE(H) or GATE(H)-to-GATE(L) delay (from CS51312 data sheet Electrical Characteristics section); FSW = switching frequency. The total power dissipation in the synchronous (lower) MOSFET can then be calculated as:
PLFET(TOTAL) + PRMSL ) PSWL
where: PLFET(TOTAL) = Synchronous (lower) FET total losses; PRMSL = Switch Conduction Losses; PSWL = Switching losses. Once the total power dissipation in the synchronous FET is known the maximum FET switch junction temperature can be calculated:
TJ + TA ) (PLFET(TOTAL) RqJA)
where: PHFET(TOTAL) = total switching (upper) MOSFET losses; PRMSH = upper MOSFET switch conduction Losses; PSWH(ON) = upper MOSFET switch-on losses; PSWH(OFF) = upper MOSFET switch-off losses. Once the total power dissipation in the switching FET is known, the maximum FET switch junction temperature can be calculated:
TJ + TA ) (PHFET(TOTAL) RqJA)
where: TJ = MOSFET junction temperature; TA = ambient temperature; PLFET(TOTAL) = total synchronous (lower) FET losses; RJA = lower FET junction-to-ambient thermal resistance.
Step 8: Control IC Power Dissipation
where: TJ = FET junction temperature; TA = ambient temperature; PHFET(TOTAL) = total switching (upper) FET losses; RJA = upper FET junction-to-ambient thermal resistance.
Step 7b: Selection of the Synchronous (Lower) FET
The power dissipation of the IC varies with the MOSFETs used, VCC, and the CS51312 operating frequency. The average MOSFET gate charge current typically dominates the control IC power dissipation. The IC power dissipation is determined by the formula:
PCONTROLIC + ICC1VCC1 ) PGATE(H) ) PGATE(L)
The switch conduction losses for the lower FET can be calculated as follows:
PRMSL + IRMS2 + IOUT RDS(ON) (1.0 * D) 2 RDS(ON)
where: PCONTROLIC = control IC power dissipation; ICC1 = IC quiescent supply current; VCC1 = IC supply voltage; PGATE(H) = upper MOSFET gate driver (IC) losses; PGATE(L) = lower MOSFET gate driver (IC) losses.
where: PRMSL = lower MOSFET conduction losses; IOUT = load current;
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The upper (switching) MOSFET gate driver (IC) losses are:
PGATE(H) + QGATE(H) FSW VGATE(H)
CS51312 R2 C1 R1 12 GATE(L) To Synchronous FET 16 COMP CCOMP
where: PGATE(H) = upper MOSFET gate driver (IC) losses; QGATE(H) = total upper MOSFET gate charge; FSW = switching frequency; VGATE(H) = upper MOSFET gate voltage. The lower (synchronous) MOSFET gate driver (IC) losses are:
PGATE(L) + QGATE(L) FSW VGATE(L)
Figure 14. Small RC Filter Provides the Proper Voltage Ramp at the Beginning of Each On-Time Cycle
where: PGATE(L) = lower MOSFET gate driver (IC) losses; QGATE(L) = total lower MOSFET gate charge; FSW = switching frequency; VGATE(L) = lower MOSFET gate voltage. The junction temperature of the control IC is primarily a function of the PCB layout, since most of the heat is removed through the traces connected to the pins of the IC.
Step 9: Slope Compensation
The artificial voltage ramp created by the slope compensation scheme results in improved control loop stability provided that the RC filter time constant is smaller than the off-time cycle duration (time during which the lower MOSFET is conducting). It is important that the series combination of R1 and R2 is high enough in resistance to avoid loading the GATE(L) pin.
Step 10: Selection of Current Limit Filter Components
Voltage regulators for today's advanced processors are expected to meet very stringent load transient requirements. One of the key factors in achieving tight dynamic voltage regulation is low ESR at the CPU input supply pins. Low ESR at the regulator output results in low output voltage ripple. The consequence is, however, that there's very little voltage ramp at the control IC feedback pin (VFB) and regulator sensitivity to noise and loop instability are two undesirable effects that can surface. The performance of the CS51312-based CPU VCC(CORE) regulator is improved when a fixed amount of slope compensation is added to the output of the PWM Error Amplifier (COMP pin) during the regulator Off-Time. Referring to Figure 14, the amount of voltage ramp at the COMP pin is dependent on the gate voltage of the lower (synchronous) FET and the value of resistor divider formed by R1and R2.
VSLOPECOMP + VGATE(L) R2 R1 ) R2 1.0 * e t
*t
In some applications, the current limit comparator may falsely trigger due to noise, load transients, or high inductor ripple currents. A filter circuit such as the one shown in Figure 15 can be added to prevent this. The RC time constant of this filter is equal to (RFB + ROUT) x CSENSE. Increasing the RC time constant will reduce the sensitivity of the circuit, but increase the time required to detect an overcurrent condition. The value of RFB + ROUT should be kept to 510 or lower to avoid significant DC offsets due to the VFB and VOUT bias currents.
VIN
GATE(H)
RSENSE
+
VOUT
GATE(L)
RFB
ROUT
where: VSLOPECOMP = amount of slope added; VGATE(L) = lower MOSFET gate voltage; R1, R2 = voltage divider resistors; t = tOFF (switch off-time); = RC constant determined by C1 and the parallel combination of R1, R2 (Figure 14), neglecting the low driver output impedance.
VFB CSENSE VOUT
Figure 15. Current Limit Filter Circuit
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"DROOP" RESISTOR FOR ADAPTIVE VOLTAGE POSITIONING AND CURRENT LIMIT Adaptive voltage positioning is used to help keep the output voltage within specification during load transients. To implement adaptive voltage positioning a "Droop Resistor" must be connected between the output inductor and output capacitors and load. This resistor carries the full load current and should be chosen so that both DC and AC tolerance limits are met. In order to determine the droop resistor value the nominal voltage drop across it at full load has to be calculated. This voltage drop has to be such that the output voltage at full load is above the minimum DC tolerance spec:
VDAC(MIN) * VDC(MIN) VDROOP(TYP) + 1.0 ) RDROOP(TOLERANCE) Current Limit 2) Mismatch Due to L/W
The variation in L/W is governed by variations due to the PCB manufacturing process. The error due to L/W mismatch is typically 1.0%. Due to I2 x R power losses the surface temperature of the droop resistor will increase causing the resistance to increase. Also, the ambient temperature variation will contribute to the increase of the resistance, according to the formula:
R + R20[1.0 ) a20(T * 20)] 3) Thermal Considerations
The current limit setpoint has to be higher than the normal full load current. Attention has to be paid to the current rating of the external power components as these are the first to fail during an overload condition. The MOSFET continuous and pulsed drain current rating at a given case temperature has to be accounted for when setting the current limit trip point.
Nominal Current Limit Setpoint
where: R20 = resistance at 20C; = 0.00393/C T= operating temperature; R = desired droop resistor value. For temperature T = 50C, the % R change = 12%.
Droop Resistor Tolerance
Tolerance due to sheet resistivity variation Tolerance due to L/W error Tolerance due to temperature variation Total tolerance for droop resistor
8.0% 1.0% 12% 21%
From the overcurrent detection data in the electrical characteristics table:
VTH(TYP) + 86 mV ICL(NOM) + R VTH(TYP) SENSE(NOM)
Droop Resistor Length, Width, and Thickness
The minimum width and thickness of the droop resistor should primarily be determined on the basis of the current-carrying capacity required, and the maximum permissible droop resistor temperature rise. PCB manufacturer design charts can be used in determining current-carrying capacity and sizes of etched copper conductors for various temperature rises above ambient. THERMAL MANAGEMENT
Thermal Considerations for Power MOSFETs
Design Rules for Using a Droop Resistor
The basic equation for laying an embedded resistor is:
RAR + o L or R + o A L (W t)
where: A = W x t = cross-sectional area; = the copper resistivity (-mil); L = length (mils); W = width (mils); t = thickness (mils). An embedded PC trace resistor has the distinct advantage of near zero cost implementation. However, this droop resistor can vary due to three reasons: 1) the sheet resistivity variation caused by variation in the thickness of the PCB layer; 2) the mismatch of L/W; and 3) temperature variation.
1) Sheet Resistivity
In order to maintain good reliability, the junction temperature of the semiconductor components should be kept to a maximum of 150C or lower. The thermal impedance (junction to ambient) required to meet this requirement can be calculated as follows:
T * TA Thermal Impedance + J(MAX) Power
A heatsink may be added to TO-220 components to reduce their thermal impedance. A number of PC board layout techniques such as thermal vias and additional copper foil area can be used to improve the power handling capability of surface mount components. EMI MANAGEMENT As a consequence of large currents being turned on and off at high frequency, switching regulators generate noise as a consequence of their normal operation. When designing for compliance with EMI/EMC regulations, additional components may be added to reduce noise emissions. These
For one ounce copper, the thickness variation is typically 1.26 mil to 1.48 mil. Therefore the error due to sheet resistivity is:
1.48 * 1.26 +" 8.0% 1.37
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components are not required for regulator operation and experimental results may allow them to be eliminated. The input filter inductor may not be required because bulk filter and bypass capacitors, as well as other loads located on the board will tend to reduce regulator di/dt effects on the circuit board and input power supply. Placement of the power component to minimize routing distance will also help to reduce emissions. LAYOUT GUIDELINES When laying out the CPU buck regulator on a printed circuit board, the following checklist should be used to ensure proper operation of the CS51312. 1. Rapid changes in voltage across parasitic capacitors and abrupt changes in current in parasitic inductors are major concerns for a good layout. 2. Keep high currents out of sensitive ground connections. 3. Avoid ground loops as they pick up noise. Use star or single point grounding. 4. For high power buck regulators on double-sided PCBs a single ground plane (usually the bottom) is recommended. 5. Even though double sided PCBs are usually sufficient for a good layout, four-layer PCBs are the optimum approach to reducing susceptibility to noise. Use the two internal layers as the power and GND planes, the top layer for power connections and component vias, and the bottom layer for the noise sensitive traces. 6. Keep the inductor switching node small by placing the output inductor, switching and synchronous FETs close together. 7. The MOSFET gate traces to the IC must be as short, straight, and wide as possible. 8. Use fewer, but larger output capacitors, keep the capacitors clustered, and use multiple layer traces with heavy copper to keep the parasitic resistance low. 9. Place the switching MOSFET as close to the +5.0 V input capacitors as possible. 10. Place the output capacitors as close to the load as possible. 11. Place the VFB, VOUT filter resistors (510 ) in series with the VFB and VOUT pins as close as possible to the pins. 12. Place the COFF and COMP capacitors as close as possible to the COFF and COMP pins. 13. Place the current limit filter capacitor between the VFB and VOUT pins, as close as possible to the pins. 14. Connect the filter components of the following pins: VFB, VOUT, COFF, and COMP to the GND pin with a single trace, and connect this local GND trace to the output capacitor GND. 15. The "Droop" Resistor (embedded PCB trace) has to be wide enough to carry the full load current. 16. Place the VCC bypass capacitor as close as possible to the IC.
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+12 V +5.0 V
1.0 F 680 pF
1200 F/10 V x 3
10 k COFF COMP 100 VID0 VID1 VID2 VID3 VID4 GND VCC1 VCC2 GATE(H) GATE(L) CS51312 VFB VOUT OVP PWRGD 0.1 F 510 510 FS70VSJ-03 1200 F/10 V x 5 VCC(CORE) 2.0 V @ 19 A
0.01 F
0.1 F
FS70VSJ-03 1.2 H 3.3 m
OVP PWRGD
Figure 16. Additional Application Circuit, 5.0 V/12 V to 2.0 V/19 A Converter
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CS51312
PACKAGE DIMENSIONS
SO-16 D SUFFIX CASE 751B-05 ISSUE J
-A-
16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019
-B-
1 8
P
8 PL
0.25 (0.010)
M
B
S
G F
K C -T-
SEATING PLANE
R
X 45 _
M D
16 PL M
J
0.25 (0.010)
TB
S
A
S
PACKAGE THERMAL DATA Parameter RJC RJA Typical Typical SO-16 28 115 Unit C/W C/W
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CS51312
Notes
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CS51312
V2 is a trademark of Switch Power, Inc. Pentium is a registered trademark of Intel Corporation.
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CS51312/D

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